The disclosed invention is directed generally to testing system for performing output propagation delay testing of digital integrated circuits, and more particularly to a test system for testing all output propagation delays concurrently.
A digital integrated circuit is typically designed such that each output is specified to have a worst case propagation delay relative to one or more predetermined inputs. More particularly, the response of each output is characterized relative to logic level transitions of one or more inputs for different logic level transitions at the output. The specified worst case propagation delays for different outputs will typically be different from each other.
Propagation delay testing is commonly performed with automatic test equipment which (1) applies input signals, (2) strobes the outputs to sample the output values, and (3) compares the sampled output values with expected values. Since the number of different strobes (i.e., strobes that occur at different times) that can be provided will typically be less than the number of different output propagation delays of a digital integrated circuit having a large number of outputs, many outputs cannot be accurately tested since many outputs are strobed after their specified worst case propagation times.